SMP + Celery 900/100fsb/128K + bp6

Blueneko · Post by **Blueneko** » Mon Sep 30, 2002 3:38 pm

Quick question, Think the bp6 will do dual celery 900 with powerleap adapter?

RRLedford · Post by **RRLedford** » Mon Sep 30, 2002 9:43 pm

CELE1=>SMP capable Cele2=>NOT SMP capable
Cele1=>566Mhz OC to 600+MHz max Cele2=>1100Mhz OC to 1200+ Max
Cele1=>128K cache Cele2=>128K cache
Neo370 socket adapter needed
Cele3=>not BP6 compatible

P-III/1100E=>SMP capable; 1100MHz OC to 1200+MHz; 256K cache

Blueneko · Post by **Blueneko** » Tue Oct 01, 2002 8:43 am

So no new celeron(s) are smp capable, if i were to use dual 800 or something like that (with 100 fsb, not 133) correct?

Blueneko · Post by **Blueneko** » Tue Oct 01, 2002 8:47 am

I spotted some celeron with the p3 core, (green chippy with the itsy bitsy blue fc design, not the newer p4 core on a green chippie, that has the larger core newer processors have.,....
these are useless? (for dual cpu)

RRLedford · Post by **RRLedford** » Tue Oct 01, 2002 10:08 am

No CELEs newer than the original CELE1s are SMP capable to my knowledge.

No posting on the BP6 community website has ever indicated this.
Perhaps some new undiscovered chip with this feature has appeared.

If so, you should declare yourself as the discoverer this CPU and make immediate claim to it, for use in all your BP6 system(s)!!

Blueneko · Post by **Blueneko** » Tue Oct 01, 2002 1:16 pm

Ok here take a look for yourself, I was looking on ebay, heres a not so old celery with the same looking p3 core, well Im pretty sure its the same core, but with less cache, I did own a celeron 1 ghz with 256k cache and it did have a larger core than this one does. SO does it actually have a p3 core?? I do believe so (maybe)

http://cgi.ebay.com/ws/eBayISAPI.dll?Vi ... 2058645851
I mean I do work in computer field, but I have been doing more research for these kinds of things.

RRLedford · Post by **RRLedford** » Tue Oct 01, 2002 1:52 pm

Don't ever trust the pictures on E-Bay as a valid indication of anything!

If the silicon die part of the chip you are looking at is the small P3 size, then the picture is almost certainly a .13micron piece of silicon, or a P3 picture being used to sell a Cele2, or a Cele3 being wrongly described.

I'd look at the Intel website tables of all processors to see if any Celeron CPU is spec'ed for SMP. Well maybe it could run SMP, even though Intel would delibertly not say so.

Blueneko · Post by **Blueneko** » Tue Oct 01, 2002 2:54 pm

so a .13 micron processor wouldnt work in a bp6, would a .18 work?

Blueneko · Post by **Blueneko** » Tue Oct 01, 2002 3:04 pm

hmm

http://www.intel.com/support/processors ... tti002.htm

man I need a break from all this thinking arh

RRLedford · Post by **RRLedford** » Wed Oct 02, 2002 8:17 am

fossil wrote:Ok...Almost any P3 coppermine (.18 micron) will work in smp BUT ONLY WITH HEAVY MODIFICATION of the BP6. Worth it??? .

I would say RISKY MODIFICATION, just soldering (1) wire per CPU & cutting one trace per adapter does not qualify as heavy.

If capacitors & voltage regulators must also be replaced, it gets HEAVY.

RRLedford · Post by **RRLedford** » Wed Oct 02, 2002 9:54 pm

I'm talking about just using a pair of Neo370s.
Many may still have to do the component upgrade soldering too, if the 2nd CPU overloads the power delivery circuits of the BP6.

Blueneko · Post by **Blueneko** » Sun Oct 13, 2002 12:07 pm

Has anyone ever tried to make a celeron 800/128K cache run in smp mode?

Blueneko · Post by **Blueneko** » Sun Oct 13, 2002 12:18 pm

0.18 micron yay

Intel® Celeron® Processor 1.10 GHz
1 GHz
950 MHz
990 MHz
850 MHz
800 MHz
Aug. 31, 2001
1.10 GHz
1 GHz
950 MHz

Jul. 2, 2001
900 MHz

May 21, 2001
850 MHz

Jan. 3, 2001
800 MHz 0.18-micron 128 KB Advanced Transfer L2 cache 100 MHz Value PCs

PDR60 · Post by **PDR60** » Sun Oct 13, 2002 12:40 pm

Why do you guys keep asking the same question????? THE ONLY CELERON THAT CAN SMP ON THE BP6 IS THE ORIGINAL CELERON WITH SPEED TOPPING OUT AT 533MHZ.
This has been answered in this thread about 3 times, whats the problem. RTFM!!!!

Blueneko · Post by **Blueneko** » Sun Oct 13, 2002 12:45 pm

wasnt the first intel chip said not to be supported in smp?

InactiveX · Post by **InactiveX** » Mon Oct 14, 2002 7:20 am

OK Here's the deal.

The original Celerons worked in SMP only if you re-routed certain pins to the motherboard socket. The original people to run Celerons in dual did this by modding the CPU sockets. Then the BP6 came out, which in effect had the pins re-routed for you.

The Celeron 2 and later will never do SMP because certain vital CPU pins have been physically separated from the CPU core.

Intels' plans have always been for the Celeron to be crippled, to preserve the higher margins on Pentiums and Xeons. When they realised that the original Celeron could be easily enabled for SMP, they went one step further and separated the SMP pins from the die.

So the party was over

RRLedford · Post by **RRLedford** » Mon Oct 14, 2002 8:29 am

InactiveX,
Thanks so much for making this so perfectly clear! Perhaps this should be a must read item before people can participate on the BP6 website?